This invention relates generally to techniques for packaging circuit elements and, more particularly, to techniques for packaging multiple integrated-circuit (IC) chips in high-density configurations.
A wide variety of techniques are available for packaging various circuit elements, including integrated-circuit (IC) chips. One conventional IC chip packaging technique employs a dual-inline (DIP) package or a leadless or a leaded chip carrier for packaging a single IC chip. Contact areas located around the periphery of the IC chip are connected to leads or pins located around the periphery of the chip package by bonding extremely fine wires between the contact areas and the leads or pins. The DIP package or chip carrier is then connected to a circuit board by the pins or by soldering.
Another conventional IC chip packaging technique is tape-automated bonding. Tape-automated bonding utilizes patterned conductors on a polymer tape for interconnecting an IC chip with a substrate or circuit board. As an example, a two-layer tape can be fabricated by depositing a metal layer onto a polymer film. The metal layer is then photolithographically patterned and etched to form a patterned conductor layer. The polymer film is also photolithographically patterned and etched to provide bonding windows for both inner and outer leads. The inner leads extend into an inner window and are bonded to the IC chip contact areas, while the outer leads extend outward from the tape and are bonded to contact areas on the substrate or circuit board. The inner and outer leads are bonded to the contact areas using a conventional bonding technique, such as thermocompression bonding, ultrasonic bonding or laser spot welding. The exposed surface of the IC chip is usually encapsulated with a silicone or epoxy material after the inner leads are bonded to the IC chip. The two-layer tape can also be fabricated by spraying a polymer layer onto a metal foil rather than by depositing a metal layer onto a polymer film. A three-layer tape can be fabricated by gluing a metal foil to a prepunched polymer film.
However, these two packaging techniques result in chip to chip interconnect lengths that greatly exceed the chip size. Consequently, interconnect delay times tend to dominate chip delay times, thus limiting the maximum operating frequencies of the chips. Interconnection lengths are important at frequencies above about 50MHz, since wiring must be treated as resistive transmission lines, which causes delays that are proportional to the square of the distance between the chips. In addition, the large circuit spread necessitated by the individual chip packages and low wiring density require large chip output drivers, which consume a large fraction of the system power.
One technique for packaging multiple IC chips in high-density configurations is flip-chip bonding. Flip-chip bonding is a packaging technique in which the IC chips are inverted and bonded face down to substrate interconnection patterns. Raised metallic bumps of solder are typically formed on the chip contact areas, which, through reflow soldering, bond the chip contact areas to their corresponding contact areas on the substrate patterns. Although flip-chip bonding does provide high-density packaging of IC chips, this technique limits heat dissipation, since the chip is not in direct contact with the substrate, and precludes visual inspection of the soldered connections.
Another technique for packaging multiple IC chips in high-density configurations has been developed by General Electric Corporation and is disclosed in a paper by Levinson, L.M. et al. entitled "High-Density Interconnects Using Laser Lithography." This packaging technique employs a high-density interconnect for packaging the chips. The high-density interconnect is fabricated by bonding a thin flexible polymer film to one or more IC chips mounted on a substrate in a chip package. Via holes are then laser drilled down through the polymer film to the chip contact areas. A metal layer is deposited on the polymer film to fill the vias holes and make electrical contact with the chip contact areas. The metal layer is then photolithographically patterned and etched to form a patterned conductor layer. Successive layers are built up by spraying or spinning on additional polymer layers and depositing additional metal layers which are subsequently photolithographically patterned and etched to form patterned conductor layers. Additional via holes are drilled and filled with metal to make electrical connections between the layers. Contact areas are formed on the uppermost layer and wire bonded to the package leads.
Although the GE high-density interconnect does provide high-density packaging of IC chips, it has several disadvantages. One disadvantage is that the interconnect is not suitable for testing IC chips, since it is not easily removed if one or more of the chips are found defective and must be replaced. Another disadvantage is that the interconnect is formed in the chip package, thus subjecting the IC chips to the fabrication process and requiring customization of the interconnect for any deviations in the locations of the chip contact areas. Accordingly, there is a need for a high-density packaging technique that does not suffer from these limitations. The present invention clearly fulfills this need.